1. Field of the Invention
This invention relates to an integrated circuit and more particularly to a flash EPROM circuit with redundancy columns and method for manufacturing same.
2. Background of the Relevant Art
Programmable read only memories (PROM) and technologies associated therewith are well-known. PROMs can be formed in either bipolar or MOS technology. Bipolar PROMs generally are programmed using fusible-link techniques. Conversely, MOS devices can employ several reversible writing procedures in order to update their programmability. Accordingly, MOS PROMs can be formed using one of three currently available technologies: EPROM, EEPROM or flash EPROM.
EPROM devices have three characteristic features. EPROMs are non-volatile, can be bulk-erased via ultraviolet light, and generally require only a single transistor in each memory cell. As such, EPROMs can be re-programmed by passing the monolithic circuit through an ultraviolet light in order for the user to re-define a stored program therein. Pulling the EPROM device from the system and subjecting it to ultraviolet light is often cumbersome as witnessed by the advent of electrically erasable devices (referred to as "EEPROM"). EEPROMs generally require both a select transistor as well as the programmable storage transistor for each cell. The select transistor can be either separate from or part of the storage transistor. In either case, each cell of an EEPROM device is generally larger than a cell of an EPROM device. Accordingly, EEPROMs storage media is less dense than EPROM, and EEPROMs are classified as not having bulk-erase capability. Instead, EEPROMs can be byte-erased and can, in many instances, operate at conventional 5-volt levels.
In order to obtain some advantages found in both EPROMs and EEPROMs, flash EPROMs were developed. Flash EPROMs utilize a single transistor for each cell. Accordingly, flash EPROM cells do not have an independent controllable select gate in addition to a control gate for selecting and controlling digital memory stored in each cell. Thus, flash EPROMs appear similar to EPROM technology. Instead of being erased via ultraviolet light, flash EPROMs are electrically erasable--similar to EEPROM technology. Still further, flash EPROMs are bulk-erased instead of byte-erased.
Program and erase of a flash EPROM can be achieved using well known technologies such as: (i) floating gate tunnel oxide, (ii) textured poly, (iii) metal nitrite oxide silicon (MNOS), and (iv) EPROM-tunnel oxide (ETOX). Floating gate tunnel oxide is a popular program and erase technology and consists of a floating gate transistor with a thin oxide grown over the drain region. Programming (moving electrons into the floating gate) is achieved by biasing the control gate, while erasure (moving electrons out of the floating gate) is achieved by biasing the drain. Electron transfer is achieved through a thin tunnel oxide separating the drain from the floating gate. The tunnel oxide only exists in a small area overlying the drain and adjacent a thicker gate oxide. Textured poly generally utilizes three layers of polysilicon which overlap in order to form three transistors in series. Programming is achieved by electrons tunneling from a first polysilicon to a second polysilicon, whereas erase is achieved by electrons tunneling from the second polysilicon to a third polysilicon. Metal nitrite oxide silicon (MNOS) consists of a single transistor with a dielectric stack of silicon nitride on top of a thin layer of oxide, wherein the oxide is placed upon the silicon substrate. Unlike floating gate technology, charge of the MNOS device is stored in discrete traps in the bulk of the nitride. A comparison of floating gate tunnel oxide, textured poly, and MNOS technologies is described by S. Lai et al., "Comparison and Trends in Today's Dominant E.sup.2 Technologies," Int'l Electron Devices Meeting Tech. Digest, (1986) pp. 580-583 (herein incorporated by reference).
More recent advances in flash EPROM technology has led to EPROM-tunnel oxide (ETOX) fabrication. Being less complicated than its predecessor, ETOX is more reliable to manufacture and can achieve high density and reproduceability. ETOX consists generally of a floating gate placed over a tunnel oxide, wherein the tunnel oxide is formed on the surface of the substrate and between source and drain regions. A control gate is placed above the floating gate and spaced therefrom by a dielectric. The source and drain regions are implanted generally perpendicular to the upper surface of the substrate, allowing the source and drain regions to slightly extend in a lateral direction beneath the floating gate outer edges. Electron transfer is achieved through the tunnel oxide region between the source and/or drain and the corresponding floating gate. A description of ETOX technology is provided by K. Robinson, "Endurance Brightens the Future of Flash --Flash Memory as a Viable Mask-Storage Alternative," Electronic Component News (November, 1988) pp. 167-169 (herein incorporated by reference).
Regardless of whether the flash EPROM device is formed according to floating gate tunnel oxide, textured poly, MNOS, or ETOX technology, there are numerous lithography steps needed to produce floating gate, control gate, tunneling area, etc., within a dense array of programmable transistors. In particular, it is important that as many transistors as possible be placed within a small array. Typically, this requires that word and bit lines be closely spaced to one another and that the plurality of programmable transistors which are coupled to the word and bit lines be formed with little tolerance to mis-alignment. In an effort to overcome misalignment and bird-beak encroachment problems often associated with field oxide mis-alignment with overlying polysilicon, as shown in U.S. Pat. No. 5,101,250 to Arima et al. (herein incorporated by reference), self-aligned source regions have gained in importance as a mechanism for overcoming such problems. Exemplary self-aligned source etch and implant technology is shown in U.S. Pat. No. 5,120,671 to Tang et al. (herein incorporated by reference).
Oftentimes, self-aligned source regions experience difficulties in etching and fully removing the field oxide overlying the source area. Plasma etching of the silicon dioxide is sometimes poorly selective to resist etching thereby causing resist residue (polymers) to deposit upon the substrate which is to receive source implant. The residue may hinder source implant, resulting in a decrease in the erase window area, a decrease in erase window overlap capacitance with the floating gate and, through voltage division, a higher erase field and faster erase. Voltage division refers to the series connection between the control gate, floating gate and silicon substrate. Furthermore, plasma etching of the silicon dioxide may also isotropically etch the field oxide in a lateral direction causing undercutting of the overlying polysilicon and thereby increasing the implant window area. An enlarged window area should be avoided if possible since it may cause additional lateral diffusion of the implanted impurities underneath the floating gate. Any additional lateral diffusion would add to the tunneling area, decreasing the erase field through voltage division, thereby forcing a slower erase of certain programmable transistors within the array. Uneven erase may cause some cells to be erased very quickly, causing other transistor cells to be forced in a depletion mode, and leaving still other cells non-erased. It is therefore important that the threshold levels of each erased cell be carefully controlled so that each cell operates at substantially the same program and erase voltage. Any enhancement or undercutting of the implant window would have a deleterious effect on those thresholds.
Not only is it important to closely monitor the etch process to ensure the etch is optimally complete (that no residue remains), but it is also important that the etch procedures used in the self-aligned sources throughout the flash EPROM array be simultaneously applied to redundancy select areas adjacent the array. Many flash EPROM devices incorporate a redundancy column or row arranged adjacent the array. A redundancy select transistor can be used to programmably select a redundant or spare row (or column) in lieu of a defective row (or column) within the array. The redundant row or column is advantageously used after the monolithic circuit is formed in order to salvage what would normally be a defective monolithic circuit. Redundancy is a well known concept in memory devices, and must be taken into account when forming a flash EPROM with self-aligned source regions. The redundancy select transistor may also have self-aligned source regions, and it is preferred that self-aligned sources of the redundancy select areas be etched and implanted during the same process steps in which the self-aligned sources of the core array are etched and implanted, respectively. If the core array and redundancy source areas are etched and implanted in separate steps, two separate masks are required to achieve the stated result. Added masking steps and lithography procedures adds to the complexity and cost of the resulting circuit. It would therefore be advantageous to combine the redundancy select area masking with the core area masking in order to reduce the overall costs of the resulting circuit. Combining the masking steps with self-aligned source etch and diffusion in both the redundancy select area and core area would provide yet a further advantage.